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CS4398 120 dB, 192 kHz Multi-Bit DAC with Volume Control
Features
Advanced Multi-bit Delta-Sigma Architecture
- 120 dB Dynamic Range - -107 dB THD+N - Low Clock Jitter Sensitivity - Differential Analog Outputs - 1.8 V to 5 V Control Data Input
Direct Stream Digital (DSD)
- Dedicated DSD Input Pins - On-chip 50 kHz Filter to Meet Scarlet Book SACD Recommendations - Matched PCM and DSD Analog Output Levels - Non-decimating Volume Control with 1/2 dB Step Size and Soft Ramp - DSD Mute Detection - Supports Phase Modulated Inputs - Optional Direct DSD Path to On Chip Switched Capacitor Filter
PCM input
- 102 dB of Stopband Attenuation - Supports Aample Rates up to 192 kHz - Accepts up to 24 bit Audio Data - Supports All Industry Standard Audio Interface Formats - Selectable Digital Filter Response - Volume Control with 1/2 dB Step Size and Soft Ramp - Flexible Channel Routing and Mixing - Selectable De-Emphasis
Control Output for External Muting
- Independent Mute Controls for Left and Right - Supports Auto Detection of Mute Output Polarity
Typical Applications
- DVD Players - SACD Players - A/V Receivers - Professional Audio Products
Supports Stand Alone or IC/SPI Configuration Embedded Level Translators
- 1.8 V to 5 V Serial Audio Input
I
3.3 V to 5 V
5V
1.8 V to 5 V Level Translator MUX Hardware or I2C/SPI Control Data MUX
Register/Hardware Configuration
Interpolation Filter with Volume Control
Multibit Modulator
Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter External Mute Control Internal Voltage Reference
Left Differential Output
1.8 V to 5V
Level Translator
PCM Input
PCM Serial Interface
Interpolation Filter with Volume Control
MUX
Multibit Modulator
Right Differential Output
MUX
DSD Input
DSD Interface
DSD Processor -Volume control -50kHz filter
Direct DSD
Left and Right Mute Controls
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2004 (All Rights Reserved)
Sep `04 DS568PP3
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Stand Alone Mode Features
Selectable Oversampling Modes
- 32 kHz to 54 kHz Sampling Rates - 50 kHz to 108 kHz Sampling Rates - 100 kHz to 216 kHz Sampling Rates
Description
The CS4398 is a complete stereo 24 bit/192 kHz digitalto-analog system. This D/A system includes digital deemphasis, half dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters followed by an oversampled multi-bit deltasigma modulator which includes mismatch shaping technology that eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor stage and low pass filter with differential analog outputs. The CS4398 also has an proprietary DSD processor which allows for volume control and 50 kHz on chip filtering without an intermediate decimation stage. It also offers an optional path for direct DSD conversion by directly using the multi-element switched capacitor array. The CS4398 accepts PCM data at sample rates from 32 kHz to 216 kHz, DSD audio data, has selectable digital filters, consumes little power, and delivers excellent sound quality. ORDERING INFORMATION Model CS4398-CZ CS4398-CZZ Lead Free CDB4398 Temp Range -10 to 70 C -10 to 70 C Description 28-pin TSSOP 28-pin TSSOP Evaluation Board
Selectable Serial Audio Interface Formats
- Left Justified, up to 24-bit - IS, up to 24 bit - Right Justified 16 bit - Right Justified 24 bit
Auto Mute Output Polarity Detect Auto Mute on Static PCM Samples 44.1 kHz 50/15 s De-Emphasis Available Soft Volume Ramp-up After Reset is Released
Control Port Mode Features
Selectable Oversampling Modes
- 32 kHz to 54 kHz Sampling Rates - 50 kHz to 108 kHz Sampling Rates - 100 kHz to 216 kHz Sampling Rates
Selectable Serial Audio Interface Formats
- Left Justified, up to 24-bit - IS, up to 24 bit - Right Justified 16 bit - Right Justified 18 bit - Right Justified 20 bit - Right Justified 24 bit
Direct Stream Digital Mode Selectable Auto or Manual Mute Polarity Selectable Interpolation Filters Selectable 32, 44.1, and 48 kHz DeEmphasis Configurable ATAPI Mixing Functions Configurable Volume and Muting Controls
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TABLE OF CONTENTS
1. PINOUT DRAWING ................................................................................................................ 6 2. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 8 SPECIFIED OPERATING CONDITIONS ................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8 ANALOG CHARACTERISTICS................................................................................................ 9 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 10 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 11 DSD COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE.......................... 11 SWITCHING CHARACTERISTICS ........................................................................................ 12 SWITCHING CHARACTERISTICS - DSD ............................................................................. 14 SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ................................ 15 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 16 DIGITAL INTERFACE SPECIFICATIONS ............................................................................. 17 3. TYPICAL CONNECTION DIAGRAM .................................................................................. 18 4. APPLICATIONS ..................................................................................................................... 19 4.1 Grounding and Power Supply Decoupling ....................................................................... 19 4.2 Analog Output and Filtering ............................................................................................. 19 4.3 The MUTEC Outputs ....................................................................................................... 19 4.4 Oversampling Modes ....................................................................................................... 20 4.5 Master and Serial Clock Ratios ....................................................................................... 20 4.6 Stand Alone Mode Settings ............................................................................................. 20 4.7 Control Port Mode ........................................................................................................... 22 5. CONTROL PORT INTERFACE ............................................................................................. 24 5.1 Memory Address Pointer (MAP) ...................................................................................... 24 5.2 Enabling the Control Port ................................................................................................ 24 5.3 Format Selection ............................................................................................................. 24 5.4 IC Format ....................................................................................................................... 24 5.5 SPI Format ...................................................................................................................... 25 6. REGISTER QUICK REFERENCE .......................................................................................... 27 7. REGISTER DESCRIPTION .................................................................................................... 28 7.1 Chip ID - Register 01h ...................................................................................................... 28 7.2 Mode Control 1 - Register 02h ......................................................................................... 28 7.3 Volume Mixing and Inversion Control - Register 03h ....................................................... 30 7.4 Mute Control - Register 04h ............................................................................................. 32 7.5 Channel A Volume Control - Register 05h ....................................................................... 33 7.6 Channel B Volume Control - Register 06h ....................................................................... 33 7.7 Ramp and Filter Control - Register 07h ............................................................................ 33 7.8 Misc. Control - Register 08h ............................................................................................. 36 7.9 Misc. Control - Register 09h ............................................................................................. 37 8. PARAMETER DEFINITIONS .................................................................................................. 38 9. REFERENCES ........................................................................................................................ 38 10. PACKAGE DIMENSIONS .................................................................................................... 39 10.1 28-TSSOP ..................................................................................................................... 39 11. APPENDIX ....................................................................................................................... 40
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Contacting Cirrus Logic Support
IMPORTANT NOTICE
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor. Purchase of IC Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips IC Patent Rights to use those components in a standard IC system. I
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Table 1. Revision History Release A1 PP1 Date November 2002 July 2003 Changes Initial Release -Updated Legal Notice on page 4. -Moved Min/Max/Typ spec note from "ANALOG CHARACTERISTICS" (on page 9) to "CHARACTERISTICS AND SPECIFICATIONS" on page 8. -Changed heading "RECOMMENDED OPERATING CONDITIONS" to "SPECIFIED OPERATING CONDITIONS" on page 8. -Updated Fullscale Output Specifications on page 9 -Updated FILT+ nominal Voltage Specification on page 17 -Added control port note to Table 2 on page 20 -Added 64x MCLK ratio note to Table 3 on page 21 -Changed default value of DIF0 in register 02h on page 27 and -Updated the definition of the "Digital Volume Control (VOL7:0) Bits 7-0" on page 33 -Updated front page block diagram -Updated front page THD+N spec -Added Note for -CZZ package option -Updated Legal Notice -Corrected 768x mode in tables 2 and 3 to use MCLKDIV2 -Added note for 0 dB-SACD to ANALOG CHARACTERISTICS -Updated Typ and Max THD+N specs -Updated Fullscale output levels -Updated VIL spec -Updated VOH and VOL levels and conditions -Updated Max sample rate specs -Updated recommended FILT+ capacitor value in Typical Connection Diagram -Corrected ATAPI table values 19d and 23d Updated DS w/ lead-free device ordering info.
PP2
February 2004
PP3
Sep 2004
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1. PINOUT DRAWING
DSD_B DSD_SCLK SDIN SCLK LRCK MCLK VD DGND M3 (AD1/CDIN) M2 (SCL/CCLK) M1 (SDA/CDOUT) M0 (AD0/CS) RST VLC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 1. Pinout Drawing
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DSD_A VLS VQ AMUTEC AOUTAAOUTA+ VA AGND AOUTB+ AOUTBBMUTEC VREF REF_GND FILT+
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Pin Name
DSD_A DSD_B DSD_SCLK SDIN SCLK LRCK MCLK VD DGND RST VLC FILT+ REF_GND VREF BMUTEC AMUTEC
# 28 1 2 3 4 5 6 7 8 13 14 15 16 17 18 25
Pin Description
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface. Serial Audio Data Input (Input) - Input for two's complement serial audio data. Serial Clock (Input) - Serial clock for the serial audio interface. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Digital Power (Input) - Positive power for the digital section. Digital Ground (Input) - Ground reference for the digital section. Reset (Input) - The device enters system reset when enabled. Control Port Power (Input) - Positive power for Control Port I/O. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Reference Ground (Input) - Ground reference for the internal sampling circuits. Voltage Reference (Input) - Positive voltage reference for the internal sampling circuits. Mute Control (Output) - The Mute Control pin is active during power-up initialization, muting, powerdown or if the master clock to left/right clock frequency ratio is incorrect. During reset these outputs are set to a high impedance. Differential Right Channel Analog Output (Output) - The full scale differential analog output level is specified in the Analog Characteristics specification table.
AOUTB+ 20 AOUTB19 AGND 21 Analog Ground (Input) - Ground reference for the analog section. VA 22 Analog Power (Input) - Positive power for the analog section. AOUTA+ 23 Differential Left Channel Analog Output (Output) - The full scale differential analog output level is AOUTA24 specified in the Analog Characteristics specification table. VQ 26 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VLS 27 Serial Audio Interface Power (Input) - Positive power for serial audio interface I/O. Stand Alone Mode Definitions M3 9 Mode Selection (Input) - Determines the operational mode of the device. M2 10 M1 11 M0 12
Control Port Mode Definitions AD1/CDIN 9 Address Bit 1 (IC) / Control Data Input (SPI) (Input) - AD1 is a chip address pin in IC mode; CDIN is the input data line for the Control Port interface in SPI mode. SCL/CCLK 10 Serial Control Port Clock (Input) - Serial clock for the serial Control Port. SDA/CDOUT 11 Serial Control Data (IC) / Control Data Output (SPI) (Input/Output) - SDA is a data I/O line in IC mode. CDOUT is the output data line for the Control Port interface in SPI mode. 12 Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC mode; CS AD0/CS is the chip select signal for SPI format.
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2. CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics are derived from measurements taken at TA = 25 C, VA = 5.0 V, VD = 3.3 V.)
SPECIFIED OPERATING CONDITIONS (AGND = 0 V; all voltages with respect to ground.)
Parameters DC Power Supply Analog power Voltage reference Digital power Serial audio interface power Control port interface power -CZ & -CZZ Symbol VA VREF VD VLS VLC TA Min 4.75 4.75 3.1 1.7 1.7 -10 Typ 5.0 5.0 3.3 3.3 3.3 Max 5.25 5.25 5.25 5.25 5.25 70 Units V V V V V C
Specified Temperature Range
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to ground.)
Parameters Analog power Voltage reference Digital power Serial audio interface power Control port interface power Input Current any pin except supplies Digital Input Voltage Serial audio interface Control port interface Ambient Operating Temperature (power applied) Storage Temperature DC Power Supply Symbol VA VREF VD VLS VLC Iin VIN-LS VIN-LC TA Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -65 Max 6.0 6.0 6.0 6.0 6.0 10 VLS+ 0.4 VLC+ 0.4 125 150 Units V V V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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ANALOG CHARACTERISTICS
(Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load RL = 1 k, CL = 10 pF.) Parameter Dynamic Range (Note 1) 24-bit A-Weighted unweighted 16-bit A-Weighted (Note 2) unweighted 24-bit 16-bit (Note 2) Idle Channel Noise / Signal-to-noise ratio Dynamic Performance - Direct DSD Dynamic Range (Note 3) Total Harmonic Distortion + Noise A-Weighted unweighted (Note 3) THD+N 0 dB -20 dB -60 dB (1 kHz) ICGM 111 108 PCM, DSD processor Direct DSD mode ZOUT RL CL 132%*VA 94%*VA 117 114 -104 -94 -54 100 0.1 100 134%*VA 96%*VA 50 1 100 -98 136%*VA 98%*VA dB dB dB dB dB dB dB ppm/C Vpp Vpp k pF (Note 1) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB Symbol Min 114 111 Typ 120 117 97 94 -107 -97 -57 -94 -74 -34 120 Max -100 Unit dB dB dB dB dB dB dB dB dB dB dB Dynamic Performance - All PCM modes and DSD Processor mode
Total Harmonic Distortion + Noise
Dynamic Performance for All Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full Scale Differential Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance
Notes: 1. One-half LSB of triangular PDF dither is added to data. 2. Performance limited by 16-bit quantization noise. 3. DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index.
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) (See note 9.)
Fast Roll-Off Parameter Min Typ Max Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz (Note 5) Passband (Note 6) to -0.01 dB corner 0 .454 to -3 dB corner 0 .499 Frequency Response 10 Hz to 20 kHz -0.01 +0.01 StopBand 0.547 StopBand Attenuation (Note 7) 102 Group Delay 9.4/Fs De-emphasis Error (Note 8) Fs = 32 kHz 0.23 (Relative to 1 kHz) Fs = 44.1 kHz 0.14 Fs = 48 kHz 0.09 Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96 kHz (Note 5) Passband (Note 6) to -0.01 dB corner 0 .430 to -3 dB corner 0 .499 Frequency Response 10 Hz to 20 kHz -0.01 0.01 StopBand .583 StopBand Attenuation (Note 7) 80 Group Delay 4.6/Fs Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192 kHz (Note 5) Passband (Note 6) to -0.01 dB corner 0 .105 to -3 dB corner 0 .490 Frequency Response 10 Hz to 20 kHz -0.01 0.01 StopBand .635 StopBand Attenuation (Note 7) 90 Group Delay 4.7/Fs Notes: 4. Slow Roll-off interpolation filter is only available in Control Port mode. 5. Filter response is guaranteed by design. 6. Response is clock dependent and will scale with Fs. 7. For Single Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Double Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 8. De-emphasis is available only in Single Speed Mode; Only 44.1 kHz De-emphasis is available in stand alone mode. 9. Amplitude vs. Frequency plots of this data are available in "Appendix" on page 40. Unit Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (cont.)
Parameter Single Speed Mode - 48 kHz (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 8) (Relative to 1 kHz) Double Speed Mode - 96 kHz (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Quad Speed Mode - 192 kHz (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Slow Roll-Off (Note 4) Min Typ Max to -0.01 dB corner to -3 dB corner (Note 7) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz to -0.01 dB corner to -3 dB corner (Note 7) to -0.01 dB corner to -3 dB corner (Note 7) 0 0 -0.01 .583 64 0 0 -0.01 .792 70 0 0 -0.01 .868 75 6.65/Fs 3.9/Fs 4.2/Fs 0.417 0.499 +0.01 0.23 0.14 0.09 .296 .499 0.01 .104 .481 0.01 Unit Fs Fs dB Fs dB s dB dB dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s
DSD COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE
Parameter DSD Processor mode (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz Roll-off Direct DSD mode (Note 5) Passband (Note 6) Frequency Response 10 Hz to 20 kHz Min to -3 dB corner 0 -0.05 27 0 0 -0.1 Typ Max 50 0.05 26.9 176.4 0 Unit kHz dB dB/Oct kHz kHz dB
to -0.1 dB corner to -3 dB corner
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SWITCHING CHARACTERISTICS (Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 20 pF)
Parameters Input Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs Min 30 50 100 40% 45% tsclkl tsclkh Single Speed Mode Double Speed Mode Quad Speed Mode SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time tsclkw tsclkw tsclkw tslrd tslrs tsdlrs tsdh 20 20
1 -------------------( 128 )Fs 1 ----------------( 64 )Fs 2 ----------------MCLK
Typ 50 -
Max 54 108 216 60% 55% -
Units kHz kHz kHz
MCLK Frequency MCLK Duty Cycle LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period
See Tables 2 & 3 (page 20) for compatible frequencies
ns ns ns ns ns ns ns ns ns
20 20 22 20
LR C K t slrd t slrs t sclkl t sclkh
S C LK t sdlrs S D ATA t sdh
Figure 2. Serial Mode Input Timing
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LR C K SCLK
Left C ha nnel
R ig h t C ha n nel
SDATA
M SB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
M SB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 3. Format 0 - Left Justified up to 24-bit Data
LR C K SCLK
Left C ha nnel
R ig h t C ha n nel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 4. Format 1 - IS up to 24-bit Data
LR C K
L e ft C h a n ne l
R ig h t C h a n n e l
SC LK
SD ATA
LS B
MS B-1 -2 -3 -4 -5 -6
B +6 +5 +4 +3 +2 +1 LS
MS -1 -2 -3 -4 -5 -6 B
B +6 +5 +4 +3 +2 +1 LS
3 2 c lo cks
Figure 5. Format 2, Right Justified 16-Bit Data. Format 3, Right Justified 24-Bit Data. Format 4, Right Justified 20-Bit Data. (Available in Control Port Mode only) Format 5, Right Justified 18-Bit Data. (Available in Control Port Mode only)
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SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VLS Volts;
CL = 20 pF) Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency Symbol tsclkl tsclkh Min 40 160 160 1.024 2.048 20 20 -20 Typ Max 60 3.2 6.4 20 Unit % ns ns MHz MHz ns ns ns
(64x Oversampled) (128x Oversampled) DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising to DSD_A or DSD_B hold time DSD clock to data transition (Phase Modulation mode)
tsdlrs tsdh tdpm
t t sclkl
sclkh
DSD _SC LK t sdlrs t sdh
DSD_A,DSD_B
Figure 6. Direct Stream Digital - Serial Audio Input Timing
t
dpm
t
dpm
D SD_SC LK (1 2 8 F s )
D SD_SC LK (6 4 F s )
DSD_A, DSD_B
Figure 7. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation mode
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SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
Logic 0 = GND, Logic 1 = VLC, CL = 20 pF) Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 10) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc, trc tfc, tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns s s s s s s ns s ns s ns (Inputs:
Notes: 10. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST t S top irs R e p e a te d S t a rt S t a rt S top t rd t fd
SDA t buf t t hdst high t hdst t fc t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t
rc
Figure 8. Control Port Timing - IC Format
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 20 pF) Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Transition time from CCLK to CDOUT valid Time from CS rising to CDOUT high-Z (Note 12) (Note 13) (Note 13) (Note 14) (Note 15) (Note 11) Symbol fsclk tsrs tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 tscdov tcscdo Min 500 500 1.0 20 66 66 40 15 Max 6 100 100 40 20 Unit MHz ns ns s ns ns ns ns ns ns ns ns ns
Notes: 11. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times. 12. Data must be held for sufficient time to bridge the transition time of CCLK. 13. For FSCK < 1 MHz. 14. CDOUT should not be sampled during this time period. 15. This time is by design and not tested.
RST
t srs
CS t sp i CCLK t r2
C D IN
t css
t scl
t sch
t csh
t f2
t dsu
t dh
CDOUT
H i-Im pedance
t
scdov
t
scdo v
t cscd o
Figure 9. Control Port Timing - SPI Format (Read/Write)
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DC ELECTRICAL CHARACTERISTICS
Parameters Normal Operation (Note 16) Power Supply Current VA= 5 V (Note 17) Vref= 5 V VD = 5 V VD = 3.3 V Interface current (Note 18) VA = 5 V, VD = 5 V VA = 5 V, VD = 3.3 V Ipd VA = 5 V, VD = 5 V VA = 5 V, VD = 3.3 V (1 kHz) (60 Hz) PSRR VQ IQmax (Note 21) VOH VOL Symbol IA Iref ID ID ILC ILS Min Typ 25 1.5 25 18 2 80 258 192 200 1 1 60 40 0.5*VA 1 0.93*VA 3 VA 0 Max 28 2 38 27 340 240 Units mA mA mA mA A A mW mW A mW mW dB dB V A V mA V V
Power Dissipation Power Down Mode (Note 19) Power Supply Current Power Dissipation All Modes of Operation Power Supply Rejection Ratio (Note 20) Common Mode Voltage Max Current draw from VQ FILT+ Nominal Voltage Maximum MUTEC Drive Current MUTEC High-Level Output Voltage MUTEC Low-Level Output Voltage
Notes: 16. Normal operation is defined as RST pin = High with a 997 Hz, 0 dBFS input sampled at the highest Fs for each speed mode, and open outputs, unless otherwise specified. 17. IA measured with no loading on the AMUTEC and BMUTEC pins. 18. ILC measured with no external loading on pin 11 (SDA). 19. Power down mode is defined as RST pin = Low with all clock and data lines held static. 20. Valid with the recommended capacitor values on FILT+ and VQ as shown in the "Typical Connection Diagram" on page 18. 21. This current is sourced/sinked directly from the VA supply.
DIGITAL INTERFACE SPECIFICATIONS
Parameters Input Leakage Current Input Capacitance High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IOH = -1.2 mA) Low-Level Output Voltage (IOL = 1.2 mA) MUTEC auto detect input high voltage MUTEC auto detect input low voltage Serial I/O Control I/O Serial I/O Control I/O Control I/O Control I/O Symbol Iin VIH VIH VIL VIL VOH VOL Min 70% 70% 80% 70% 30% Typ 8 Max 10 30% 30% 20% Units A pF VLS VLC VLS VLC VLC VLC VA VA
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3. TYPICAL CONNECTION DIAGRAM
+3.3V to +5V
10 uF
0.1 uF
0.1 uF 10 uF
+5V
VD
System Clock
VA
MCLK
PCM Digital Audio Source
AMUTEC AOUTA AOUTA+
Left Channel Analog Conditioning and Mute
SCLK LRCK SDIN VLS DSD_SCLK
+1.8V to 0.1 uF +5V
DSD Audio Source
AOUTB+ AOUTB BMUTEC
Right Channel Analog Conditioning and Mute
DSD_A DSD_B
+1.8V to 0.1 uF +5V
CS4398
VLC M0 (AD0/CS) Controler M1 (SDA/CDOUT) M2 (SCL/CCLK) M3 (AD1/CDIN) RST DGND AGND REF_GND
0.1 uF 33 uF
VQ FILT+
0.1 uF 100 uF 3.3 uF
or stand alone pull-ups/ downs
VREF VA
Figure 10. Typical Connection Diagram
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4. APPLICATIONS 4.1 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4398 requires careful attention to power supply and grounding arrangements to optimize performance. The Typical Connection Diagram shows the recommended power arrangement with VA, VD, VLS and VLC connected to clean supplies. Decoupling capacitors should be located as close to the device package as possible. If desired, all supply pins may be connected to the same supply, but the recommended decoupling capacitors should still be placed on each supply pin. The AGND and DGND pins should be tied together with solid ground plane fill underneath the converter extending out to the GND side of the decoupling caps for VA, VD, VREF, and FILT+. This recommended layout can be seen in the CDB4398 evaluation board and datasheet.
4.2 Analog Output and Filtering
The Cirrus Logic application note "Design Notes for a 2-Pole Filter with Differential Input" (AN48) discusses the second-order Butterworth filter and differential to single-ended converter topology which was implemented on the CS4398 evaluation board, CDB4398, as seen in Figure 11. The CS4398 does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
Figure 11. Recommended Output Filter
4.3 The MUTEC Outputs
The AMUTEC and BMUTEC pins have an auto-polarity detect feature. The MUTEC output pins are high impedance at the time of reset. The external mute circuitry needs to be self biased into an active state in order to be muted during reset. Upon release of reset, the CS4398 will detect the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive when the mutes become active. The external-bias voltage level that the MUTEC pins see at the time of release of reset must meet the "MUTEC auto detect input high/low voltage" specs as outlined in the Digital Characteristics in section 2. Figure 12 shows a single example of both an active high and an active low mute drive circuit. In these designs, the pull-up and pull-down resistors have been especially chosen to meet the input high/low threshold when used with the MMUN2111 and MMUN2211 internal bias resistances of 10k Ohms. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
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Figure 12. Recommended Mute Circuitry
4.4 Oversampling Modes
The CS4398 operates in one of three oversampling modes based on the input sample rate. Single-Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
4.5 Master and Serial Clock Ratios
The required MCLK-to-LRCK ratio and suggested SCLK-to-LRCK ratio are outlined in table 2. MCLK can be at any phase in regards to LRCK and SCLK. SCLK, LRCK and SDATA must meet the phase and timing relationships outlined in Section 2. Some common MCLK frequencies have been outlined in table 3. Table 2. Clock Ratios MCLK/LRCK Single Speed Double Speed 256, 384, 512, 768*, 1024*, 1152* 128, 192, 256, 384, 512* 64 Quad Speed 96 128, 256* 192 SCLK/LRCK 32, 48, 64, 96, 128 32, 48, 64 32 (16 bits only) 32, 48 32, 64 32, 48, 64, 96 LRCK Fs Fs Fs Fs Fs Fs
*These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit.
4.6 Stand Alone Mode Settings
In stand alone mode (also referred to as "hardware mode") the device is configured using the M0 through M3 pins. These pins must be connected to either the VLC supply or ground. The Interface format is set by pins M0 and M1. The sample rate range/oversampling mode (Single/Double/Quad Speed mode) and de-emphasis are set by pins M2 and M3. The settings can be found in Tables 4 and 5.
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Table 3. Common Clock Frequencies Mode Sample MCLK (MHz) (sampleRate MCLKDIV2 MCLKDIV3 rate range) (kHz) MCLK Ratio 256x 384x 512x 768x 1024x 1152x 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 Single Speed (32 to 50 kHz) 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 MCLK Ratio 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 Double Speed (50 to 100 kHz) 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 MCLK Ratio 64x* 96x 128x 192x 256x 176.4 11.2896* 16.9344 22.5792 33.8688 45.1584 Quad Speed (100 to 200 kHz) 192 12.2880* 18.4320 24.5760 36.8640 49.1520 These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit. * This MCLK ratio limits the audio word length to 16 bits; see Table 2 on page 20 Table 4. Digital Interface Format, Stand Alone Mode Options DESCRIPTION FORMAT Left Justified, up to 24-bit data 0 IS, up to 24-bit data 1 Right Justified, 16-bit Data 2 Right Justified, 24-bit Data 3 Table 5. Mode Selection, Stand Alone Mode Options DESCRIPTION Single-Speed without De-Emphasis (32 to 50 kHz sample rates) Single-Speed with 44.1 kHz De-Emphasis; see Figure 17 on page 29 Double-Speed (50 to 100 kHz sample rates) Quad-Speed (100 to 200 kHz sample rates)
M1 0 0 1 1
M0 0 1 0 1
FIGURE 3 4 5 5
M3 0 0 1 1
M2 0 1 0 1
The following features are always enabled in stand alone mode: Auto-mute on zero data, Auto MUTEC polarity detect, ramp volume from mute to 0dB by 1/8th dB steps every LRCK (soft ramp) after reset or clock mode change, and the fast roll-off interpolation filter is used. The following features are not available in stand alone mode: DSD mode, Right Justified 20 and 18 bit serial audio interfaces, MCLK divide by 2 and MCLK divide by 3 (allows 1024 and 1152 clock ratios), slow roll-off interpolation filter, volume control, ATAPI mixing, 48 kHz and 32 kHz de-emphasis, and all other features enabled by registers that are not mentioned above.
4.6.1 Recommended Power-up Sequence (Stand Alone Mode)
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the Control Port is reset to its default settings. 2. Bring RST high. The device will remain in a low power state and will initiate the stand alone power-up sequence following approximately 218 MCLK cycles.
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4.7 Control Port Mode 4.7.1 Recommended Power-up Sequence (Control Port Mode)
1. Hold RST low until the power supply, master, and left/right clocks are stable. In this state, the Control Port is reset to its default settings. 2. Bring RST high. Set the CPEN bit (Reg. 8h) prior to the completion of the stand alone power-up sequence (approximately 218 MCLK cycles). Setting this bit will halt the stand alone power-up sequence and initialize the Control Port to its default settings. The desired register settings can be loaded while keeping the PDN bit (Reg. 8h) set to 1. 3. Clear the PDN bit to initiate the power-up sequence. If the CPEN bit is not written within the allotted time, the device will startup in stand-alone mode and begin converting data according to the current state of the M0 to M3 pins. Since these pins are also the control port pins an undesired mode may be entered. For this reason, if the CPEN bit is not set before the allotted time elapses, the SDIN line must be kept at static 0 (not dithered) until the device is properly configured. This will keep the device from converting data improperly.
4.7.2 Sample Rate Range/Oversampling Mode (Control Port Mode)
Sample rate mode selection is determined by the FM bits (Reg. 02h).
4.7.3 Serial Audio Interface Formats (Control Port Mode)
The desired serial audio interface format is selected using the DIF2:0 bits (Reg. 02h).
4.7.4 MUTEC Pins (Control Port Mode)
The auto-mute polarity feature (mentioned in Section 4.3) is defeatable. The MUTEP1:0 bits in register 04h give the option to over-ride the mute polarity which was auto detected at startup (see the Register Description section for more details).
4.7.5 Interpolation Filter (Control Port Mode)
To accommodate the increasingly complex requirements of digital audio systems, the CS4398 incorporates selectable interpolation filters. A fast and a slow roll-off filter are available in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate a variety of musical tastes and styles. The FILT_SEL bit (Reg. 07h) is used to select which filter is used (see the Register Description section for more details). Filter specifications can be found in Section 2, and filter response plots can be found in Figures 20 to 43 in "Appendix" on page 40.
4.7.6 Direct Stream Digital (DSD) Mode (Control Port Mode)
In control-port mode the FM bits (Reg. 02h) are used to configure the device for DSD mode. The DIF bits (Reg 02h) then control the expected DSD rate and MCLK ratio. The DSD_SRC bit (Reg. 02h) selects the input pins for DSD clocks and data. During DSD operation, the PCM related pins should either be tied low or remain active with clocks. When the DSD related pins are not being used they should either be tied low, or remain active with clocks. The DIR_DSD bit (Reg 07h) selects between two proprietary methods for DSD to analog conversion. The first method uses a decimation free DSD processing technique which allows for features such as matched PCM level output, DSD volume control, and 50 kHz on chip filter. The second method sends the DSD data directly to the on-chip switched-capacitor filter for conversion (without the above mentioned features).
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The DSD_PM_EN bit (Reg. 09h) selects Phase Modulation (data plus data inverted) as the style of data input. In this mode the DSD_PM_mode bit selects whether a 128Fs or 64x clock is used for phase modulated 64x data (see Figure 13). Use of phase modulation mode may not directly effect the performance of the CS4398, but may lower the sensitivity to board level routing of the DSD data signals. The CS4398 can detect errors in the DSD data which does not comply to the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 09h) allow the CS4398 to alter the incoming invalid DSD data. Depending on the error, the data may either be attenuated or replaced with a muted DSD signal (the MUTEC pins would set according to the DAMUTE bit (Reg. 04h)). More information for any of these register bits can be found in the Register Description section. The DSD input structure and analog outputs are designed to handle a nominal 0 dB-SACD (50% modulation index) at full rated performance. Signals of +3 dB-SACD may be applied for brief periods of time however, performance at these levels is not guaranteed. If sustained +3 dB-SACD levels are required, the digital volume control should be set to -3.0 dB. This same volume control register affects PCM output levels. There is no need to change the volume control setting between PCM and DSD in order to have the 0 dB output levels match (both 0 dBFS and 0 dB-SACD will output at -3 dB in this case).
D S D N orm al M ode
D S D P hase M odulation M ode BCKA D S D _S C LK (128Fs)
D S D _S C LK
BCKA (64Fs)
BCKD D S D _S C LK (64Fs)
D0
D1
D1
D2
D S D _A , D S D _B
D S D _A , D S D _B
D0
D1
D2
Figure 13. DSD phase modulation mode diagram
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5. CONTROL PORT INTERFACE
The Control Port is used to load all the internal settings. The operation of the Control Port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain static if no operation is required.
5.1 Memory Address Pointer (MAP) 5.1.1 Memory Address Pointer (MAP) Register Detail
7 INCR 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 MAP3 0 2 MAP2 0 1 MAP1 0 0 MAP0 0
5.1.2 INCR (Auto Map Increment Enable)
Default = `0' 0 - Disabled, the MAP will stay constant for successive writes 1 - Enabled, the MAP will auto increment after each byte is written, allowing block reads or writes of successive registers
5.1.3 MAP3-0 (Memory Address Pointer)
Default = `0000'
5.2 Enabling the Control Port
On the CS4398 the Control Port pins are shared with stand alone configuration pins. To enable the Control Port, the user must set the CPEN bit. This is done by performing an IC or SPI write. Once the Control Port is enabled, these pins are dedicated to Control Port functionality. To prevent audible artifacts the CPEN bit (see Section 7) should be set prior to the completion of the stand alone power-up sequence, approximately 218 MCLK cycles. Setting this bit will halt the stand alone power-up sequence and initialize the Control Port to its default settings. Note, the CPEN bit can be set any time after RST goes high; however, setting this bit after the stand alone power-up sequence has completed can cause audible artifacts.
5.3 Format Selection
The Control Port has 2 formats: SPI and IC, with the CS4398 operating as a slave device. If IC operation is desired, AD0/CS should be tied to VLC or GND. If the CS4398 ever detects a high to low transition on AD0/CS after power-up, SPI format will automatically be selected.
5.4 IC Format
In IC Format, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with a clock to data relationship as shown in Figure 14. The receiving device should send an acknowledge (ACK) after each byte received. There is no CS pin. Pins AD0 and AD1 form the partial chip address and should be tied to VLC or GND as required. The upper 5 bits of the 7 bit address field must be 10011.
5.4.1 Writing in IC Format
To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the chip address. The eighth bit of the address byte is the R/W bit (low for a write). The next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then followed by the data to be written. To write multiple registers, continue providing a clock and data, waiting for the CS4398 to acknowledge between each byte. To end the transaction, send a STOP condition.
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5.4.2 Reading in IC Format
To communicate with the CS4398, initiate a START condition of the bus (see Figure 14.). Next, send the chip address. The eighth bit of the address byte is the R/W bit (high for a read). The contents of the register pointed to by the MAP will be output after the chip address. To read multiple registers, continue providing a clock and issue an ACK after each byte. To end the transaction, send a STOP condition.
N o te 1 SDA
10011 AD1 AD0 R /W ACK DATA 1-8 ACK DATA 1-8 ACK
SCL
S ta rt
S to p
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
Figure 14. Control Port Timing, IC Format
5.5 SPI Format
In SPI format, CS is the CS4398 chip select signal, CCLK is the Control Port bit clock, CDIN is the input data line from the microcontroller, CDOUT is the output data line and the chip address is 1001100. CS, CCLK and CDIN are all inputs and data is clocked in on the rising edge of CCLK. CDOUT is an output and is high impedance when not actively outputting data.
5.5.1 Writing in SPI
Figure 15 shows the operation of the Control Port in SPI format. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write indicator (R/W), which must be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into register designated by the MAP. To write multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high.
CS
CCLK
CHIP ADDRESS CDIN 1001100 R/W MAP MSB byte 1 MAP = Memory Address Pointer DATA LSB byte n
Figure 15. Control Port Timing, SPI Format (Write)
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5.5.2 Reading in SPI
Figure 16 shows the operation of the Control Port in SPI format. To read to a register, bring CS low. The first 7 bits on CDIN form the chip address and must be 1001100. The eighth bit is a read/write control (R/W), which must be high to read. The CDOUT line will then output the data from the register designated by the MAP. To read multiple registers, keep CS low and continue providing clocks on CCLK. End the read transaction by setting CS high. The CDOUT line will go to a high impedance state once CS goes high.
CS
C C LK
C H IP ADDRESS C D IN 1001100 R /W
D AT A
CDOUT MSB b yte 1 b y te n LSB
Figure 16. Control Port Timing, SPI Format (Read)
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6.
Addr
1h
REGISTER QUICK REFERENCE
Function
Chip ID
7
6
5
4
3
2
REV2 DEM0 0 ATAPI2
1
REV1 FM1 0 ATAPI1
0
REV0 FM0 0 ATAPI0
PART4 PART3 PART1 PART0 PART2 0 1 1 0 default 1 2h Mode Control DSD_SRC DIF2 DIF0 DEM1 DIF1 0 0 0 0 default 0 3h Volume, Mixing, VOLB=A INVERTA INVERTB ATAPI4 ATAPI3 and Inversion Control 0 0 0 0 1 default 4h Mute Control PAMUTE DAMUTE MUTEC A=B MUTE_A MUTE_B 1 1 0 0 0 default 5h Channel A Volume VOL7 VOL6 VOL5 VOL4 VOL3 Control 0 0 0 0 0 default 6h Channel B Volume VOL7 VOL6 VOL5 VOL4 VOL3 Control 0 0 0 0 0 default 7h Ramp and Filter SZC1 SZC0 RMP_UP RMP_DN Reserved Control 1 0 1 1 0 default 8h Misc. Control PDN CPEN FREEZE MCLKDIV2 MCLKDIV3 1 0 0 0 0 default 9h Misc. Control 2 Reserved Reserved Reserved Reserved STATIC_ DSD 0 0 0 0 1 default
0 Reserved 0 VOL2 0 VOL2 0 FILT_SEL
0 MUTEP1 0 VOL1 0 VOL1 0 Reserved
1 MUTEP0 0 VOL0 0 VOL0 0 DIR_DSD
0 0 0 Reserved Reserved Reserved 0 0 0 INVALID_ DSD_PM_MODE DSD_PM_EN DSD 0 0 0
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7.
7.1
REGISTER DESCRIPTION
Chip ID - Register 01h
7 PART4 0 6 PART3 1 5 PART2 4 PART1 1 3 PART0 0 2 REV2 1 REV1 0 REV0 -
** All register access is R/W unless specified otherwise**
1
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 01110b (14h) and the remaining Bits (2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
7.2
Mode Control 1 - Register 02h
6 DIF2 0 5 DIF1 4 DIF0 0 3 DEM1 0 2 DEM0 0 1 FM1 0 0 FM0 0
7 DSD_SRC 0
0
7.2.1
DSD INPUT SOURCE SELECT (DSD_SRC) BIT 7
Function: When set to 0 (default) the dedicated DSD pins will be the active DSD inputs. When set to 1 the source for DSD inputs will be as follows: DSDA input on SDATA pin DSDB input on LRCK pin DSD_SCLK input on SCLK pin The dedicated DSD pins must be tied low while not in use.
7.2.2
DIGITAL INTERFACE FORMAT (DIF2:0) BITS 6-4
Function: These bits select the interface format for the serial audio input. The Functional Mode bits determine whether PCM or DSD mode is selected. PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 3 through 5. Table 6. Digital Interface Formats - PCM Mode DIF2
0 0 0 0 1 1 1 1
DIF1
0 0 1 1 0 0 1 1
DIF0
0 1 0 1 0 1 0 1
DESCRIPTION Left Justified, up to 24-bit data IS, up to 24-bit data Right Justified, 16-bit data Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 18-bit data Reserved Reserved
FORMAT
0 (Default) 1 2 3 4 5
FIGURE
3 4 5 5 5 5
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DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required Master Clock to DSD data rate is defined by the Digital Interface Format pins. Table 7. Digital Interface Formats - DSD Mode DIF2 0 0 0 0 1 1 1 1 DIF1 0 0 1 1 0 0 1 1 DIF0 0 1 0 1 0 1 0 1 DESCRIPTION 64x oversampled DSD data with a 4x MCLK to DSD data rate (Default) 64x oversampled DSD data with a 6x MCLK to DSD data rate 64x oversampled DSD data with a 8x MCLK to DSD data rate 64x oversampled DSD data with a 12x MCLK to DSD data rate 128x oversampled DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate
Gain dB T1=50 s 0dB
7.2.3
DE-EMPHASIS CONTROL (DEM1:0) BITS 3-2.
Default = 0 00 - No De-emphasis 01 - 44.1 kHz De-emphasis 10 - 48 kHz De-emphasis 11 - 32 kHz De-emphasis Function: Selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 kHz sample rates. (see Figure 17) Note: De-emphasis is only available in Single Speed Mode.
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 17. De-Emphasis Curve
7.2.4
FUNCTIONAL MODE (FM1:0) BITS 1-0
Default = 00 00 - Single-Speed Mode (30 to 50 kHz sample rates) 01 - Double-Speed Mode (50 to 100 kHz sample rates) 10 - Quad-Speed Mode (100 to 200 kHz sample rates) 11 - Direct Stream Digital Mode Function: Selects the required range of input sample rates or DSD Mode.
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7.3 Volume Mixing and Inversion Control - Register 03h
6 INVERT A 0 5 INVERT B 0 4 ATAPI4 0 3 ATAPI3 1 2 ATAPI2 0 1 ATAPI1 0 0 ATAPI0 1
7 VOLB=A 0
7.3.1
CHANNEL B VOLUME = CHANNEL A VOLUME (VOLB=A) BIT 7
Function: When set to 0 (default) the AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes. When set to 1 the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and Volume Control Bytes, and the B Channel Bytes are ignored.
7.3.2
INVERT SIGNAL POLARITY (INVERT_A) BIT 6
Function: When set to 1, this bit inverts the signal polarity of channel A. When set to 0 (default), this function is disabled.
7.3.3
INVERT SIGNAL POLARITY (INVERT_B) BIT 5
Function: When set to 1, this bit inverts the signal polarity of channel B. When set to 0 (default), this function is disabled.
7.3.4
ATAPI CHANNEL MIXING AND MUTING (ATAPI4:0) BITS 4-0
Default = 01001 - AOUTA=aL, AOUTB=bR (Stereo) Function: The CS4398 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 8 and Figure 18 for additional information.
Left Channel Audio Data A Channel Volume Control MUTE AoutA
Right Channel Audio Data
B Channel Volume Control
MUTE
AoutB
Figure 18. ATAPI Block Diagram 30 DS568PP3
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Table 8. ATAPI Decode ATAPI4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ATAPI3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ATAPI2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ATAPI1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ATAPI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AOUTA MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] a[(L+R)/2] MUTE MUTE MUTE MUTE aR aR aR aR aL aL aL aL [(aL+bR)/2] [(aL+bR)/2] [(bL+aR)/2] [(aL+bR)/2] AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/2]
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7.4 Mute Control - Register 04h
6 DAMUTE 1 5 MUTEC A=B 0 4 MUTE_A 0 3 MUTE_B 0 2 Reserved 0 1 MUTEP1 0 0 MUTEP0 0
7 PAMUTE 1
7.4.1
PCM AUTO-MUTE (PAMUTE) BIT 7
Function: When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. When set to 0 this function is disabled.
7.4.2
DSD AUTO-MUTE (DAMUTE) BIT 6
Function: When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 256 repeated 8-bit DSD mute patterns (as defined in the SACD specification). A single bit not fitting the repeated mute pattern (mentioned above) will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. When set to 0 this function is disabled.
7.4.3
AMUTEC = BMUTEC (MUTEC A=B) BIT 5
Function: When set to 0 (default) the AMUTEC and BMUTEC pins operate independently. When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
7.4.4
A CHANNEL MUTE (MUTE_A) BIT 4 B CHANNEL MUTE (MUTE_B) BIT 3
Function: When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any ramping due to the soft and zero cross function. When set to 0 (default) this function is disabled.
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7.4.5 MUTE POLARITY AND DETECT (MUTEP1:0) BITS 1-0
Default = 00 00 - Auto polarity detect, selected from AMUTEC pin 01 - Reserved 10 - Active low mute polarity 11 - Active high mute polarity Function: Auto mute polarity detect (00) See section 4.3 on page 19 for description. Active low mute polarity (10) When RST is low the outputs are high impedance and will need to be biased active. Once reset has been released and after this bit is set, the MUTEC output pins will be active low polarity. Active high mute polarity (11) At reset time the outputs are high impedance and will need to be biased active. Once reset has been released and after this bit is set, the MUTEC output pins will be active high polarity.
7.5 7.6
Channel A Volume Control - Register 05h Channel B Volume Control - Register 06h
7 VOL7 0 6 VOL6 0 5 VOL5 0 4 VOL4 0 3 VOL3 0 2 VOL2 0 1 VOL1 0 0 VOL0 0
7.6.1
DIGITAL VOLUME CONTROL (VOL7:0) BITS 7-0
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments from 0 to -127.5 dB. Volume settings are decoded as shown in Table 9. The volume changes are implemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. Note that the values in the volume setting column in Table 9 are approximate. The actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. Table 9. Example Digital Volume Settings
Binary Code 00000000 00000001 00000110 11111111 Decimal Value 0 1 6 255 Volume Setting 0 dB -0.5 dB -3.0 dB -127.5 dB
7.7
Ramp and Filter Control - Register 07h
7 SZC1 1 6 SZC0 0 5 RMP_UP 1 4 RMP_DN 1 3 Reserved 0 2 FILT_SEL 0 1 Reserved 0 0 DIR_DSD 0
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7.7.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC1:0) BITS 7-6
Default = 10 SZC1 SZC0 0 0 1 1 Function: Immediate Change When Immediate Change is selected all level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp PCM Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp DSD Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 512 DSD_SCLK periods (1024 periods if 128x DSD_SCLK is used). Soft Ramp and Zero Cross Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 0 1 0 1 PCM description Immediate Change Zero Cross Soft Ramp Soft Ramp on Zero Crossings DSD description Immediate Change Soft Ramp
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7.7.2 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP) BIT 5
Function: When set to 1 (default), an un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change or error, and after changing the Functional Mode. This un-mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate un-mute is performed in these instances. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
7.7.3
SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN) BIT 4
Function: When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. When set to 0, an immediate mute is performed prior to executing a filter mode change. Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
7.7.4
INTERPOLATION FILTER SELECT (FILT_SEL) BIT 2
Function: When set to 0 (default), the Interpolation Filter has a fast roll off. When set to 1, the Interpolation Filter has a slow roll off. The specifications for each filter can be found in the Analog characteristics table, and response plots can be found in figures 20 to 43 found in the "Appendix" on page 40.
7.7.5
DIRECT DSD CONVERSION (DIR_DSD) BIT 0
Function: When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control functions. When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion. In this mode the full scale DSD and PCM levels will not be matched (see Section 2), the dynamic range performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available (see section 2 for filter specifications).
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CS4398
7.8 Misc. Control - Register 08h
7 PDN 1 6 CPEN 0 5 FREEZE 0 4 MCLKDIV2 0 3 MCLKDIV3 0 2 Reserved 0 1 Reserved 0 0 Reserved 0
7.8.1
POWER DOWN (PDN) BIT 7
Function: When set to 1 (default) the entire device will enter a low-power state and the contents of the control registers will be retained. The power-down bit defaults to `1' on power-up and must be disabled before normal operation in Control Port mode can occur. This bit is ignored if CPEN is not set.
7.8.2
CONTROL PORT ENABLE (CPEN) BIT 6 Function:
This bit is set to 0 by default, allowing the device to power-up in stand alone Mode. Control Port Mode can be accessed by setting this bit to 1. This will allow operation of the device to be controlled by the registers and the pin definitions will conform to Control Port Mode.
7.8.3
FREEZE CONTROLS (FREEZE) BIT 5
Function: When set to 1, this function allows modifications to be made to the registers without the changes taking effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. When set to 0 (default), register changes take effect immediately.
7.8.4
MASTER CLOCK DIVIDE BY 2 ENABLE (MCLKDIV2) BIT 4
Function: When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged.
7.8.5
MASTER CLOCK DIVIDE BY 3 ENABLE (MCLKDIV3) BIT 3
Function: When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 3 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged.
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CS4398
7.9 Misc. Control - Register 09h
6 Reserved 0 5 Reserved 0 4 Reserved 0 3 STATIC_DSD 1 2 INVALID_DSD 0 1 DSD_PM_MODE 0 0 DSD_PM_EN 0
7 Reserved 0
7.9.1
STATIC DSD DETECT (STATIC_DSD) BIT 3
Function: When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected, sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE register. When set to 0, this function is disabled.
7.9.2
INVALID DSD DETECT (INVALID_DSD) BIT 2
Function: When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if detected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE register. When set to 0 (default), this function is disabled.
7.9.3
DSD PHASE MODULATION MODE SELECT (DSD_PM_MODE) BIT 1
Function: When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for phase modulation mode. (See Figure 13 on page 23) When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for phase modulation mode.
7.9.4
DSD PHASE MODULATION MODE ENABLE (DSD_PM_EN) BIT 0
Function: When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set accordingly. When set to 0 (default), this function is disabled (DSD normal mode).
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8. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C.
9. REFERENCES
1. CDB4398 Evaluation Board Datasheet 2. "Design Notes for a 2-Pole Filter with Differential Input". Cirrus Logic Application Note AN48 3. The IC-Bus Specification: Version 2.0" Philips Semiconductors, December 1998. http://www.semiconductors.philips.com "
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10.PACKAGE DIMENSIONS
10.1
N
28-TSSOP
D
E11 A2 A1 SEATING PLANE A
E
2
e b
L
END VIEW
SIDE VIEW
123
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03150 0.00748 0.378 BSC 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.035 0.0096 0.382 BSC 0.2519 0.1732 0.026 BSC 0.024 4
MAX 0.47 0.006 0.04 0.012 0.386 BSC 0.256 0.177 -0.029 8
MIN -0.05 0.80 0.19 9.60 BSC 6.30 4.30 -0.50 0
MILLIMETERS NOM -0.10 0.90 0.245 9.70 BSC 6.40 4.40 0.65 BSC 0.60 4
NOTE MAX 1.20 0.15 1.00 0.30 9.80 BSC 6.50 4.50 -0.75 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters. Figure 19. 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters Package Thermal Resistance (Note 4) Symbol 28-TSSOP JA JC Min Typ 37 13 Max Units C/Watt C/Watt
Notes: 4. JA is specified according to JEDEC specifications for multi-layer PCBs.
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CS4398
11.
0
APPENDIX
0
-20
-20
Amplitude (dB)
Amplitude (dB)
-40
-40
-60
-60
-80
-80
-100
-100
-120 0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
-120 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 20. Single Speed (fast) Stopband Rejection
0
Figure 21. Single Speed (fast) Transition Band
0.02
-1
0.015
-2 0.01 -3 0.005
Amplitude (dB)
Amplitude (dB)
-4
-5
0
-6
-0.005
-7 -0.01 -8 -0.015
-9
-10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
-0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 22. Single Speed (fast) Transition Band (detail)
Figure 23. Single Speed (fast) Passband Ripple
0
0
-20
-20
Amplitude (dB)
-60
Amplitude (dB)
-40
-40
-60
-80
-80
-100
-100
-120 0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
-120 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 24. Single Speed (slow) Stopband Rejection
Figure 25. Single Speed (slow) Transition Band
40
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CS4398
0
0.02
-1
0.015
-2 0.01 -3 0.005
Amplitude (dB)
Amplitude (dB)
-4
-5
0
-6
-0.005
-7 -0.01 -8 -0.015
-9
-10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
-0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 26. Single Speed (slow) Transition Band (detail)
Figure 27. Single Speed (slow) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 28. Double Speed (fast) Stopband Rejection
0
Figure 29. Double Speed (fast) Transition Band
0.02
1
0.015
2
0.01
3
Amplitude (dB)
5
Amplitude (dB)
4
0.005
0
6
0.005
7
0.01
8
9
0.015
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 30. Double Speed (fast) Transition Band (detail)
Figure 31. Double Speed (fast) Passband Ripple
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CS4398
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 32. Double Speed (slow) Stopband Rejection
0
Figure 33. Double Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15 0.2 Frequency(normalized to Fs)
0.25
0.3
0.35
Figure 34. Double Speed (slow) Transition Band (detail)
Figure 35. Double Speed (slow) Passband Ripple
0
0
20
20
40 Amplitude (dB)
Amplitude (dB)
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 36. Quad Speed (fast) Stopband Rejection
Figure 37. Quad Speed (fast) Transition Band
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CS4398
0
0.2
1
0.15
2
0.1
3
0.05
Amplitude (dB)
Amplitude (dB) 0.05 0.1 0.15 0.2
4
5
0
6
7
8
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1 0.15 Frequency(normalized to Fs)
0.2
0.25
Figure 38. Quad Speed (fast) Transition Band (detail)
Figure 39. Quad Speed (fast) Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4 0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 40. Quad Speed (slow) Stopband Rejection
0
Figure 41. Quad Speed (slow) Transition Band
0.02
1
0.015
2
0.01
3
0.005 Amplitude (dB)
Amplitude (dB)
4
5
0
6
0.005
7
0.01
8
0.015
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.02
0.04 0.06 0.08 Frequency(normalized to Fs)
0.1
0.12
Figure 42. Quad Speed (slow) Transition Band (detail)
Figure 43. Quad Speed (slow) Passband Ripple
DS568PP3
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